The Evolution of DSP Processors

The number and variety of products that include some form of digital signal processing has grown dramatically over the last five years. DSP has become a key component in many consumer, communications, medical, and industrial products. These products use a variety of hardware approaches to implement DSP, ranging from the use of off-the-shelf microprocessors to field-programmable gate arrays (FPGAs) to custom integrated circuits (ICs). Programmable " DSP processors, " a class of microprocessors optimized for DSP, are a popular solution for several reasons: They can potentially be reprogrammed in the field, allowing product upgrades or fixes. They are often more cost-effective (and less risky) than custom hardware, particularly for low-volume applications, where the development cost of custom ICs may be prohibitive. And in comparison to other types of microprocessors, DSP processors often have an advantage in terms of speed, cost, and energy efficiency. In this article, we trace the evolution of DSP processors, from early architectures to current state-of-the-art devices. We highlight some of the key differences among architectures, and compare their strengths and weaknesses. Finally, we discuss the growing class of general-purpose processors that have been enhanced to address the needs of DSP applications. From the outset, DSP processor architectures have been molded by DSP algorithms. For nearly every feature found in a DSP processor, there are associated DSP algorithms whose computation is in some way eased by inclusion of this feature. Therefore, perhaps the best way to understand the evolution of DSP architectures is to examine typical DSP algorithms and identify how their computational requirements have influenced the architectures of DSP processors. As a case study, we will consider one of the most common signal processing tasks, the FIR filter. Fast Multipliers The FIR filter is mathematically expressed as Σx*h, where x is a vector of input data, and h is a vector of filter coefficients. For each " tap " of the filter, a data sample is multiplied by a filter coefficient, with the result added to a running sum for all of the taps (for an introduction to DSP concepts and filter theory, refer to [2]). Hence, the main component of the FIR filter algorithm is